000:00.0 Intel 82443BX Host Bridge/Controller (host bridge, revision 0x03) PCI configuration registers: Common header: 0x00: 0x71908086 0x22100106 0x06000003 0x00002000 Vendor Name: Intel (0x8086) Device Name: 82443BX Host Bridge/Controller (0x7190) Command register: 0x0106 I/O space accesses: off Memory space accesses: on Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): on Fast back-to-back transactions: off Status register: 0x2210 Capability List support: on 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: off Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: on Asserted System Error (SERR): off Parity error detected: off Class Name: bridge (0x06) Subclass Name: host (0x00) Interface: 0x00 Revision ID: 0x03 BIST: 0x00 Header Type: 0x00 (0x00) Latency Timer: 0x20 Cache Line Size: 0x00 Type 0 ("normal" device) header: 0x10: 0xf4000008 0x00000000 0x00000000 0x00000000 0x20: 0x00000000 0x00000000 0x00000000 0x00000000 0x30: 0x00000000 0x000000a0 0x00000000 0x00000000 Base address register at 0x10 type: 32-bit prefetchable memory base: 0xf4000000, not sized Base address register at 0x14 not implemented(?) Base address register at 0x18 not implemented(?) Base address register at 0x1c not implemented(?) Base address register at 0x20 not implemented(?) Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x0000 Subsystem ID: 0x0000 Expansion ROM Base Address: 0x00000000 Capability list pointer: 0xa0 Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x00 (none) Interrupt line: 0x00 Capability register at 0xa0 type: 0x02 (AGP, rev. 1.0) Device-dependent header: 0x40: 0x00000000 0x00000000 0x00000000 0x00000000 0x50: 0x0000220c 0x09000000 0x11111003 0x00000000 0x60: 0x40302010 0x40404040 0xffe82a00 0x0000ffa3 0x70: 0x780a1f20 0x010f00aa 0x38dc0f03 0x00000000 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 0x90: 0x00000070 0x00006104 0x00000500 0x00000000 0xa0: 0x00100002 0x1f000203 0x00000000 0x00000000 0xb0: 0x00002080 0x00000030 0x017ce000 0x00001020 0xc0: 0x00000000 0x00000000 0x00000c18 0x00000000 0xd0: 0x02020808 0x00221202 0x0000000c 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x6000f800 0x00000f20 0x00000000 000:01.0 Intel 82443BX AGP Interface (PCI bridge, revision 0x03) PCI configuration registers: Common header: 0x00: 0x71918086 0x0220011f 0x06040003 0x00012000 Vendor Name: Intel (0x8086) Device Name: 82443BX AGP Interface (0x7191) Command register: 0x011f I/O space accesses: on Memory space accesses: on Bus mastering: on Special cycles: on MWI transactions: on Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): on Fast back-to-back transactions: off Status register: 0x0220 Capability List support: off 66 MHz capable: on User Definable Features (UDF) support: off Fast back-to-back capable: off Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: bridge (0x06) Subclass Name: PCI (0x04) Interface: 0x00 Revision ID: 0x03 BIST: 0x00 Header Type: 0x01 (0x01) Latency Timer: 0x20 Cache Line Size: 0x00 Type 1 (PCI-PCI bridge) header: 0x10: 0x00000000 0x00000000 0x20010100 0xa2a0c0c0 0x20: 0xfef0fd00 0xfbf0f800 0x00000000 0x00000000 0x30: 0x00000000 0x00000000 0x00000000 0x008c0000 Base address register at 0x10 not implemented(?) Base address register at 0x14 not implemented(?) Primary bus number: 0x00 Secondary bus number: 0x01 Subordinate bus number: 0x01 Secondary bus latency timer: 0x20 Secondary status register: 0xa2a0 66 MHz capable: on User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: medium (0x1) Signaled Target Abort: off Received Target Abort: off Received Master Abort: on System Error: off Parity Error: on I/O region: base register: 0xc0 limit register: 0xc0 base upper 16 bits register: 0x0000 limit upper 16 bits register: 0x0000 Memory region: base register: 0xfd00 limit register: 0xfef0 Prefetchable memory region: base register: 0xf800 limit register: 0xfbf0 base upper 32 bits register: 0x00000000 limit upper 32 bits register: 0x00000000 Reserved @ 0x34: 0x00000000 Expansion ROM Base Address: 0x00000000 Interrupt line: 0x00 Interrupt pin: 0x00 (none) Bridge control register: 0x008c Parity error response: off Secondary SERR forwarding: off ISA enable: on VGA enable: on Master abort reporting: off Secondary bus reset: off Fast back-to-back capable: on Device-dependent header: 0x40: 0x00000000 0x00000000 0x00000000 0x00000000 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 000:03.0 Texas Instruments PCI1225 PCI-CardBus Bridge (CardBus bridge, revision 0x01) PCI configuration registers: Common header: 0x00: 0xac1c104c 0x02100007 0x06070001 0x00822008 Vendor Name: Texas Instruments (0x104c) Device Name: PCI1225 PCI-CardBus Bridge (0xac1c) Command register: 0x0007 I/O space accesses: on Memory space accesses: on Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Status register: 0x0210 Capability List support: on 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: off Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: bridge (0x06) Subclass Name: CardBus (0x07) Interface: 0x00 Revision ID: 0x01 BIST: 0x00 Header Type: 0x02+multifunction (0x82) Latency Timer: 0x20 Cache Line Size: 0x08 Type 2 (PCI-CardBus bridge) header: 0x10: 0x40000000 0x020000a0 0x20040400 0xfffff000 0x20: 0x00000000 0xfffff000 0x00000000 0xfffffffc 0x30: 0x00000000 0xfffffffc 0x00000000 0x07c0010b 0x40: 0x008b1028 0x00000001 Base address register at 0x10 (CardBus socket/ExCA registers) type: 32-bit nonprefetchable memory base: 0x40000000, not sized Capability list pointer: 0xa0 Secondary status register: 0x0200 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: off Data parity error detection: off DEVSEL timing: medium (0x1) PCI target aborts terminate CardBus bus master transactions: off CardBus target aborts terminate PCI bus master transactions: off Bus initiator aborts terminate initiator transactions: off System error: off Parity error: off PCI bus number: 0x00 CardBus bus number: 0x04 Subordinate bus number: 0x04 CardBus latency timer: 0x20 CardBus memory region 0: base register: 0xfffff000 limit register: 0x00000000 CardBus memory region 1: base register: 0xfffff000 limit register: 0x00000000 CardBus I/O region 0: base register: 0xfffffffc limit register: 0x00000000 CardBus I/O region 1: base register: 0xfffffffc limit register: 0x00000000 Interrupt line: 0x0b Interrupt pin: 0x01 (pin A) Bridge control register: 0x07c0 Parity error response: off CardBus SERR forwarding: off ISA enable: off VGA enable: off CardBus master abort reporting: off CardBus reset: on Functional interrupts routed by ExCA registers: on Memory window 0 prefetchable: on Memory window 1 prefetchable: on Write posting enable: on Subsystem vendor ID: 0x1028 Subsystem ID: 0x008b Base address register at 0x44 (legacy-mode registers) type: i/o base: 0x00000000, not sized Capability register at 0xa0 type: 0x01 (Power Management, rev. 1.0) Device-dependent header: 0x48: 0x00000000 0x00000000 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x2024d021 0x00000000 0x00000000 0x01261222 0x90: 0x6066a6c0 0x00000000 0x00000000 0x00000000 0xa0: 0x7e210001 0x00800000 0x00000018 0x00000007 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 000:03.1 Texas Instruments PCI1225 PCI-CardBus Bridge (CardBus bridge, revision 0x01) PCI configuration registers: Common header: 0x00: 0xac1c104c 0x02100007 0x06070001 0x00822008 Vendor Name: Texas Instruments (0x104c) Device Name: PCI1225 PCI-CardBus Bridge (0xac1c) Command register: 0x0007 I/O space accesses: on Memory space accesses: on Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Status register: 0x0210 Capability List support: on 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: off Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: bridge (0x06) Subclass Name: CardBus (0x07) Interface: 0x00 Revision ID: 0x01 BIST: 0x00 Header Type: 0x02+multifunction (0x82) Latency Timer: 0x20 Cache Line Size: 0x08 Type 2 (PCI-CardBus bridge) header: 0x10: 0x40001000 0x020000a0 0x20050500 0xfffff000 0x20: 0x00000000 0xfffff000 0x00000000 0xfffffffc 0x30: 0x00000000 0xfffffffc 0x00000000 0x07c0010b 0x40: 0x008b1028 0x00000001 Base address register at 0x10 (CardBus socket/ExCA registers) type: 32-bit nonprefetchable memory base: 0x40001000, not sized Capability list pointer: 0xa0 Secondary status register: 0x0200 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: off Data parity error detection: off DEVSEL timing: medium (0x1) PCI target aborts terminate CardBus bus master transactions: off CardBus target aborts terminate PCI bus master transactions: off Bus initiator aborts terminate initiator transactions: off System error: off Parity error: off PCI bus number: 0x00 CardBus bus number: 0x05 Subordinate bus number: 0x05 CardBus latency timer: 0x20 CardBus memory region 0: base register: 0xfffff000 limit register: 0x00000000 CardBus memory region 1: base register: 0xfffff000 limit register: 0x00000000 CardBus I/O region 0: base register: 0xfffffffc limit register: 0x00000000 CardBus I/O region 1: base register: 0xfffffffc limit register: 0x00000000 Interrupt line: 0x0b Interrupt pin: 0x01 (pin A) Bridge control register: 0x07c0 Parity error response: off CardBus SERR forwarding: off ISA enable: off VGA enable: off CardBus master abort reporting: off CardBus reset: on Functional interrupts routed by ExCA registers: on Memory window 0 prefetchable: on Memory window 1 prefetchable: on Write posting enable: on Subsystem vendor ID: 0x1028 Subsystem ID: 0x008b Base address register at 0x44 (legacy-mode registers) type: i/o base: 0x00000000, not sized Capability register at 0xa0 type: 0x01 (Power Management, rev. 1.0) Device-dependent header: 0x48: 0x00000000 0x00000000 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x2024d021 0x00000000 0x00000000 0x01261222 0x90: 0x6066a6c0 0x00000000 0x00000000 0x00000000 0xa0: 0x7e210001 0x00800000 0x00000018 0x00000007 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 000:07.0 Intel 82371AB (PIIX4) PCI-ISA Bridge (miscellaneous bridge, revision 0x02) PCI configuration registers: Common header: 0x00: 0x71108086 0x0280010f 0x06800002 0x00800000 Vendor Name: Intel (0x8086) Device Name: 82371AB (PIIX4) PCI-ISA Bridge (0x7110) Command register: 0x010f I/O space accesses: on Memory space accesses: on Bus mastering: on Special cycles: on MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): on Fast back-to-back transactions: off Status register: 0x0280 Capability List support: off 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: bridge (0x06) Subclass Name: miscellaneous (0x80) Interface: 0x00 Revision ID: 0x02 BIST: 0x00 Header Type: 0x00+multifunction (0x80) Latency Timer: 0x00 Cache Line Size: 0x00 Type 0 ("normal" device) header: 0x10: 0x00000000 0x00000000 0x00000000 0x00000000 0x20: 0x00000000 0x00000000 0x00000000 0x00000000 0x30: 0x00000000 0x00000000 0x00000000 0x00000000 Base address register at 0x10 not implemented(?) Base address register at 0x14 not implemented(?) Base address register at 0x18 not implemented(?) Base address register at 0x1c not implemented(?) Base address register at 0x20 not implemented(?) Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x0000 Subsystem ID: 0x0000 Expansion ROM Base Address: 0x00000000 Reserved @ 0x34: 0x00000000 Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x00 (none) Interrupt line: 0x00 Device-dependent header: 0x40: 0x00000000 0x00000000 0x00000000 0x00320044 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x0b05050b 0x000000d2 0x0000f200 0x00000000 0x70: 0x00000000 0x0c0c0000 0x00000000 0x00000000 0x80: 0x00060000 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00814106 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000f30 0x00000000 000:07.1 Intel 82371AB (PIIX4) IDE controller (IDE mass storage, interface 0x80, revision 0x01) PCI configuration registers: Common header: 0x00: 0x71118086 0x02800005 0x01018001 0x00002000 Vendor Name: Intel (0x8086) Device Name: 82371AB (PIIX4) IDE controller (0x7111) Command register: 0x0005 I/O space accesses: on Memory space accesses: off Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Status register: 0x0280 Capability List support: off 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: mass storage (0x01) Subclass Name: IDE (0x01) Interface: 0x80 Revision ID: 0x01 BIST: 0x00 Header Type: 0x00 (0x00) Latency Timer: 0x20 Cache Line Size: 0x00 Type 0 ("normal" device) header: 0x10: 0x00000000 0x00000000 0x00000000 0x00000000 0x20: 0x00000861 0x00000000 0x00000000 0x00000000 0x30: 0x00000000 0x00000000 0x00000000 0x00000000 Base address register at 0x10 not implemented(?) Base address register at 0x14 not implemented(?) Base address register at 0x18 not implemented(?) Base address register at 0x1c not implemented(?) Base address register at 0x20 type: i/o base: 0x00000860, not sized Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x0000 Subsystem ID: 0x0000 Expansion ROM Base Address: 0x00000000 Reserved @ 0x34: 0x00000000 Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x00 (none) Interrupt line: 0x00 Device-dependent header: 0x40: 0xa307a307 0x00000000 0x02020005 0x00000000 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000f30 0x00000000 000:07.2 Intel 82371AB (PIIX4) USB Host Controller (USB serial bus, revision 0x01) PCI configuration registers: Common header: 0x00: 0x71128086 0x02800005 0x0c030001 0x00002000 Vendor Name: Intel (0x8086) Device Name: 82371AB (PIIX4) USB Host Controller (0x7112) Command register: 0x0005 I/O space accesses: on Memory space accesses: off Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Status register: 0x0280 Capability List support: off 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: serial bus (0x0c) Subclass Name: USB (0x03) Interface: 0x00 Revision ID: 0x01 BIST: 0x00 Header Type: 0x00 (0x00) Latency Timer: 0x20 Cache Line Size: 0x00 Type 0 ("normal" device) header: 0x10: 0x00000000 0x00000000 0x00000000 0x00000000 0x20: 0x0000ece1 0x00000000 0x00000000 0x00000000 0x30: 0x00000000 0x00000000 0x00000000 0x0000040b Base address register at 0x10 not implemented(?) Base address register at 0x14 not implemented(?) Base address register at 0x18 not implemented(?) Base address register at 0x1c not implemented(?) Base address register at 0x20 type: i/o base: 0x0000ece0, not sized Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x0000 Subsystem ID: 0x0000 Expansion ROM Base Address: 0x00000000 Reserved @ 0x34: 0x00000000 Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x04 (pin D) Interrupt line: 0x0b Device-dependent header: 0x40: 0x00000000 0x00000000 0x00000000 0x00000000 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x00000010 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00002000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000f30 0x00000000 000:07.3 Intel 82371AB (PIIX4) Power Management Controller (miscellaneous bridge, revision 0x02) PCI configuration registers: Common header: 0x00: 0x71138086 0x02800003 0x06800002 0x00000000 Vendor Name: Intel (0x8086) Device Name: 82371AB (PIIX4) Power Management Controller (0x7113) Command register: 0x0003 I/O space accesses: on Memory space accesses: on Bus mastering: off Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Status register: 0x0280 Capability List support: off 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: bridge (0x06) Subclass Name: miscellaneous (0x80) Interface: 0x00 Revision ID: 0x02 BIST: 0x00 Header Type: 0x00 (0x00) Latency Timer: 0x00 Cache Line Size: 0x00 Type 0 ("normal" device) header: 0x10: 0x00000000 0x00000000 0x00000000 0x00000000 0x20: 0x00000000 0x00000000 0x00000000 0x00000000 0x30: 0x00000000 0x00000000 0x00000000 0x00000000 Base address register at 0x10 not implemented(?) Base address register at 0x14 not implemented(?) Base address register at 0x18 not implemented(?) Base address register at 0x1c not implemented(?) Base address register at 0x20 not implemented(?) Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x0000 Subsystem ID: 0x0000 Expansion ROM Base Address: 0x00000000 Reserved @ 0x34: 0x00000000 Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x00 (none) Interrupt line: 0x00 Device-dependent header: 0x40: 0x00000801 0x1fbfff0f 0x00003fa4 0x00000000 0x50: 0x00055000 0x8a7d4000 0x02000067 0xd0000000 0x60: 0x626700e0 0x986f0850 0x00000000 0x00000000 0x70: 0x00170280 0x00000000 0x00000000 0x00000000 0x80: 0x00000001 0x00000000 0x00000000 0x00000000 0x90: 0x00000841 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00010000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000f30 0x00000000 001:00.0 Neomagic MagicMedia 256ZX VGA (VGA display) PCI configuration registers: Common header: 0x00: 0x000610c8 0x02900007 0x03000000 0x00802000 Vendor Name: Neomagic (0x10c8) Device Name: MagicMedia 256ZX VGA (0x0006) Command register: 0x0007 I/O space accesses: on Memory space accesses: on Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Status register: 0x0290 Capability List support: on 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: display (0x03) Subclass Name: VGA (0x00) Interface: 0x00 Revision ID: 0x00 BIST: 0x00 Header Type: 0x00+multifunction (0x80) Latency Timer: 0x20 Cache Line Size: 0x00 Type 0 ("normal" device) header: 0x10: 0xfa000008 0xfdc00000 0xfdb00000 0x00000000 0x20: 0x00000000 0x00000000 0x00000000 0x008b1028 0x30: 0x00000000 0x000000dc 0x00000000 0xff10010b Base address register at 0x10 type: 32-bit prefetchable memory base: 0xfa000000, not sized Base address register at 0x14 type: 32-bit nonprefetchable memory base: 0xfdc00000, not sized Base address register at 0x18 type: 32-bit nonprefetchable memory base: 0xfdb00000, not sized Base address register at 0x1c not implemented(?) Base address register at 0x20 not implemented(?) Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x1028 Subsystem ID: 0x008b Expansion ROM Base Address: 0x00000000 Capability list pointer: 0xdc Reserved @ 0x38: 0x00000000 Maximum Latency: 0xff Minimum Grant: 0x10 Interrupt pin: 0x01 (pin A) Interrupt line: 0x0b Capability register at 0xdc type: 0x01 (Power Management, rev. 1.0) Device-dependent header: 0x40: 0x00000000 0x00000000 0x00000000 0x00000000 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x06210001 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000 001:00.1 Neomagic MagicMedia 256ZX Audio (audio multimedia) PCI configuration registers: Common header: 0x00: 0x800610c8 0x02900000 0x04010000 0x00800000 Vendor Name: Neomagic (0x10c8) Device Name: MagicMedia 256ZX Audio (0x8006) Command register: 0x0000 I/O space accesses: off Memory space accesses: off Bus mastering: off Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Status register: 0x0290 Capability List support: on 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: medium (0x1) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: multimedia (0x04) Subclass Name: audio (0x01) Interface: 0x00 Revision ID: 0x00 BIST: 0x00 Header Type: 0x00+multifunction (0x80) Latency Timer: 0x00 Cache Line Size: 0x00 Type 0 ("normal" device) header: 0x10: 0xf9800008 0xfda00000 0x00000000 0x00000000 0x20: 0x00000000 0x00000000 0x00000000 0x008b1028 0x30: 0x00000000 0x000000dc 0x00000000 0x00000205 Base address register at 0x10 type: 32-bit prefetchable memory base: 0xf9800000, not sized Base address register at 0x14 type: 32-bit nonprefetchable memory base: 0xfda00000, not sized Base address register at 0x18 not implemented(?) Base address register at 0x1c not implemented(?) Base address register at 0x20 not implemented(?) Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x1028 Subsystem ID: 0x008b Expansion ROM Base Address: 0x00000000 Capability list pointer: 0xdc Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x02 (pin B) Interrupt line: 0x05 Capability register at 0xdc type: 0x01 (Power Management, rev. 1.0) Device-dependent header: 0x40: 0x00000000 0x00000000 0x00000000 0x00000000 0x50: 0x00000000 0x00000000 0x00000000 0x00000000 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00210001 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000